For example, the following technology is known. A superscalar processor is an arithmetic processor having four instruction pipelines. In the superscalar processor, a reorder buffer manages information relevant to four instructions that have been substantially simultaneously fetched from a main storage unit by an instruction fetch unit. The four instructions that have been fetched are simultaneously decoded by an instruction decode unit. Then, the four instructions are executed in parallel by four ALUs (Arithmetic Logical Units) while being arbitrated by an instruction issue control unit. For example, when a hardware failure occurs in one of the ALUs, a failure history flag is set. A reorder buffer manages information relevant to the instruction in which the failure has occurred. In accordance with this information, the instruction issue control unit uses the three ALUs without any failures to control the instruction fetch unit, the instruction decode unit, and the four ALUs, so that the failed instruction is executed once again.    Patent document 1: Japanese Laid-Open Patent Application No. 2000-339185    Patent document 2: Japanese Laid-Open Patent Application No. 2007-26392
When an instruction cannot be completed in one of the pipeline units in an arithmetic processor including plural pipeline units, the corresponding instruction is registered. The registered instruction is then entered into a pipeline unit operating under low load. In such a control method, it takes a long processing time to select one of the instructions among plural candidate instructions that have been registered.